Semiconductor Process Engineer Job Description

A Semiconductor Process Engineer is the person responsible for one step, or a small family of steps, in the several-hundred-step sequence that turns a bare silicon wafer into finished chips. Georgetown's Center for Security and Emerging Technology (CSET) describes the job plainly: process engineers "develop and improve the steps that ensure chips are manufactured consistently and with minimal defects." In practice that means owning a module. One engineer may own the chemical vapor deposition and atomic layer deposition steps that lay down dielectric and metal films. Another owns plasma etch, cutting contacts, trenches and spacers into those films. Others own chemical mechanical planarization, wet cleans, diffusion and anneal furnaces, or physical vapor deposition for metal layers.

The daily loop

The work runs on data. Each morning starts with the overnight statistical process control charts: film thickness, refractive index, etch rate, critical dimension, within-wafer uniformity and particle adders, one chart per chamber. A point outside the limits triggers the reaction plan, which can mean putting lots on hold, pulling a chamber down for the equipment team, or running monitor wafers to see whether the shift is real. Fault detection and classification systems watch tool sensor traces (RF reflected power, chamber pressure, gas flow, endpoint signals) and flag wafers that ran abnormally even when the measured output looked fine. The process engineer decides what those alarms mean and what happens to the material.

Bigger projects sit on top of that loop. A new product or a cost-down program brings recipe development: designed experiments over pressure, power, gas chemistry, temperature and time, measured with ellipsometry, cross-section SEM, TEM and electrical test structures. A new chamber has to be matched to its siblings so that the fab can dispatch lots to any qualified tool. A yield excursion means sorting wafer maps by tool, chamber and time until one step stands out, then proving the cause with a split lot.

Gases, chemistry and safety

Etch and deposition modules run on hazardous and high-global-warming-potential materials. EPA notes that fluorinated greenhouse gases are used both for etching circuitry features on silicon wafers and for cleaning chemical vapor deposition tool chambers. The process engineer specifies those gases in the recipe, so abatement performance, gas consumption and emissions data are part of the job alongside wafer results.

Who the engineer works with

Equipment engineers and technicians keep the hardware running; the process engineer tells them what "running correctly" means for the wafer. Process integration engineers set the targets each step has to deliver to the rest of the flow. Yield and defect engineers bring the inspection and test data that open an investigation. Metrology engineers own the measurement tools the module depends on, and field engineers from the tool vendor support upgrades and hardware fixes. Deliverables are concrete: released recipes, process specifications, control plans, change requests, excursion reports and qualification packages. In CSET's breakdown, scientists and engineers make up 39% of the overall domestic fabrication workforce, a group that CSET defines to include process engineers.

The job is an engineering role, and the usual entry point is a bachelor's degree in chemical engineering, materials science, electrical engineering or physics. Coursework that maps straight onto the work includes thermodynamics, transport phenomena, solid-state physics, plasma physics, thin-film materials and semiconductor device physics. Some engineers in development fabs and in modules where the chemistry is new hold a master's degree or PhD. ONET's Microsystems Engineers profile, the federal occupation that lists Process Engineer among its reported titles, places the work in Job Zone Five, and in ONET's survey of incumbents 34% said a master's degree was required, 31% a bachelor's degree and 22% a doctoral degree.

Skills that get used every week

• Design of experiments and statistics. Factorial and response-surface designs, analysis of variance, capability indices and control-chart rules. JMP, Minitab or Python with pandas and statsmodels are the everyday tools.
• Data access. SQL and scripting to pull lot history, tool sensor traces and metrology results out of the manufacturing execution system and engineering data warehouses.
• Materials characterization. Reading ellipsometry, X-ray fluorescence, four-point probe sheet resistance, SEM and TEM cross-sections, and defect review images.
• Equipment literacy. Enough understanding of RF matching networks, vacuum systems, mass flow controllers and endpoint detection to argue productively with the equipment team.
• Change discipline. Writing a change request, defining a qualification plan and closing it with data, because a recipe edit can touch every wafer in the fab.

Experience

New graduates can be hired straight into a module as junior process engineers, sometimes after a co-op in a fab. As a rough guide, engineers with around 3 to 5 years in a module take on recipe ownership for a full tool set, and senior engineers lead new-technology introductions or tool-set transfers between fabs. Industry experience matters: respondents to a 2023 Bureau of Industry and Security survey, as summarized by CSET, reported that engineers without prior semiconductor experience typically require one to two years of additional specialized training. Engineers moving in from chemical, pharmaceutical or display manufacturing bring transferable process control skills but still have to learn vacuum and plasma hardware and fab conventions.

Credentials

No license is required for fab process work. Some engineers take the Fundamentals of Engineering (FE) exam from the National Council of Examiners for Engineering and Surveying as an early step toward licensure. For the statistical side of the work, ASQ awards the Certified Six Sigma Black Belt (CSSBB) and Certified Six Sigma Green Belt (CSSGB). Employer-run training on specific tool platforms, cleanroom protocol and chemical safety comes with the job.

Fab process engineers have no BLS occupation of their own; the closest fit is a broad residual group, so federal projections describe a larger pool than the title. O*NET reports 166,700 people employed in Engineers, All Other in 2025, projects average growth of 3% to 4% from 2025 to 2035 and expects about 8,800 openings a year on average. Those figures cover many specialties outside semiconductors, so the investment pipeline in U.S. fabs is a more direct signal for this role.

New fabs need module owners

The CHIPS and Science Act of 2022 paired direct federal funding with a manufacturing investment tax credit, and CSET notes that the credit was increased to 35% in July 2025 through the One Big Beautiful Bill Act. CSET counts more than 140 new projects announced across the semiconductor ecosystem, totaling more than $640 billion in planned private investment across 30 states as of January 2026. Every new fab needs a full roster of module engineers before the first production lots run.

TSMC's Arizona site shows the link to AI hardware. TSMC says its first Arizona fab started high-volume production on N4 process technology in Q4 2024, and that the total investment will strengthen America's leadership in critical technologies like AI and high-performance computing. On July 16, 2026, the City of Phoenix reported that TSMC announced plans to invest an additional $100 billion to build four more fabs at 2-nanometer or more advanced nodes, bringing its total planned investment in Arizona to $265 billion across 12 facilities. These are announced plans, not finished capacity. CSET's September 2026 brief adds that the boom in data center construction for running AI models "promises to fuel demand for quite some time."

The talent pipeline is the constraint

The Semiconductor Industry Association's 2025 State of the U.S. Semiconductor Industry report, citing an SIA-Oxford Economics study, projects a shortfall of 67,000 technicians, computer scientists and engineers in the semiconductor industry by 2030. CSET also points to the industry's reliance on foreign talent: international students accounted for six in ten advanced degree graduates in semiconductor-related engineering and computer science disciplines in 2024. CSET adds that immigration reforms could expand the number of skilled workers eligible for these roles.

How AI is changing the work

AI is arriving through the data the process engineer already owns. A NIST workshop report published in November 2025 describes an industry coalition that held five roundtables between July 2023 and July 2025 around an AI and machine learning virtual metrology use case, built partly on wafer production datasets from multiple etch machines. Virtual metrology uses tool sensor data to predict what a wafer would measure, so the models depend on the sensor and metrology data the module already collects. The engineer still sets the targets, judges when a model has drifted and signs off on recipe changes.

Where the role leads

Module process engineering opens several paths: process integration, yield engineering, technology development for the next node, equipment-vendor applications engineering, and fab management through area and module manager roles.

Dear Hiring Manager,

I am applying for the Semiconductor Process Engineer opening on your thin films team. For the past four years I have owned a set of plasma-enhanced CVD chambers depositing silicon nitride and oxide films at a high-volume logic fab, and I would like to bring that module experience to your new production line.

My day starts with the control charts. I own the reaction plans for my chambers, and I rewrote two of them after noticing that our monitor-wafer frequency was catching drifts a shift too late. The change paired a fault detection rule on reflected RF power with a tighter refractive index limit, and it gave the night-shift technicians a clear decision tree instead of a page call to me.

My biggest project was matching a newly installed chamber to its siblings. I ran a designed experiment over pressure, power and gas ratio, compared film stress and wet-etch rate against the fleet, and worked with the equipment team to trace a residual uniformity offset to a showerhead spacing difference. The chamber was released to production with full dispatch freedom, and the qualification package became our template for later installs.

I also led the investigation into a recurring particle excursion at a contact etch step downstream of our films. Wafer maps pointed at us, but splitting lots across chambers and cleaning recipes showed the source was a seasoning gap after preventive maintenance. We changed the recovery procedure and the excursion did not return.

I write my own SQL and Python to pull sensor traces and metrology data, and I am comfortable presenting results to integration and yield engineers who will push back hard. I would welcome the chance to discuss how I can support your ramp.

Sincerely, Jordan Avery