Neuromorphic Engineer Job Description

A Neuromorphic Engineer builds computers that borrow their organizing ideas from the brain. Instead of a clocked processor shuttling numbers between separate memory and compute units, a neuromorphic system uses spiking neurons that fire only when something happens, with memory and processing sitting side by side. Intel describes the principles behind its Loihi 2 processor as "asynchronous, event-based spiking neural networks (SNNs), integrated memory and computing, and sparse and continuously changing connections." The engineer's job is to turn those principles into systems that solve a real problem using very little power.

The work splits into three overlapping layers, and a given job may weight one of them.

Networks. On the algorithm side, the engineer designs spiking neural networks: which neuron model to use, how information is encoded in spike timing or rate, and how the network learns. Because spikes are discrete events, standard backpropagation does not apply directly, so engineers use surrogate-gradient methods or convert a trained conventional network into spiking form, then check how much accuracy survives the conversion.

Mapping and software. A trained network still has to fit onto physical cores with fixed memory and routing. Engineers partition neurons across chips, tune spike traffic and write the glue code that moves data between a host computer and the neuromorphic board. Lava, which its documentation calls "an open-source software framework for developing neuro-inspired applications and mapping them to neuromorphic hardware," is one such toolchain; it sits on a compiler and runtime layer called Magma.

Hardware. On the silicon side, the engineer designs or verifies neuron and synapse circuits, digital or analog, then takes them through simulation, FPGA prototypes and chip bring-up. Analog circuit design is another branch of the hardware work.

Across all three layers, the scoreboard is measurement. A neuromorphic result means little without a careful comparison against a GPU or CPU doing the same task: energy per inference, latency, accuracy and how those trade off. Much of the daily work is building fair benchmarks and small reference applications. Sandia National Laboratories, for example, uses a suite of neural "mini-apps," including neuromorphic random walks, neural sparse coding and neural graph analysis, to understand and predict how neuromorphic hardware will perform.

The applications are the places where power is scarce or latency matters: satellites, drones, remote sensors and robots. Event-based vision sensors, which report changes in a scene rather than full frames, produce the kind of sparse, event-driven input that spiking processors are built to handle. National laboratories also use large neuromorphic systems for scientific simulation, including models of biological neural circuits.

The job is distinct from building GPU clusters or AI accelerators for data centers. Those engineers optimize dense matrix multiplication for large models at scale. A Neuromorphic Engineer works on sparse, event-driven computation, often on research chips with small software ecosystems, and spends real time on questions specific to the field: how to represent a signal as spikes, how to keep learning running on the chip, and whether the energy savings hold up once the whole system is measured.

Colleagues include computational neuroscientists, circuit designers, machine learning researchers, the mission or product engineers who will use the system, and the program managers who fund the work.

Neuromorphic engineering draws people from three directions: electrical and computer engineering, computer science and machine learning, and computational neuroscience or physics. A useful profile is depth in one and working fluency in the other two.

Education. As a rough guide, research-track roles at national laboratories and corporate research labs go to candidates with a PhD or a master's degree in electrical engineering, computer engineering, computer science or a related field, with a thesis or projects on spiking networks, brain-inspired circuits or emerging memory devices. A bachelor's degree with strong hardware or embedded experience can lead to engineering-support roles, such as board bring-up, test automation or software tooling for a neuromorphic platform. University groups are one training ground: the University of Tennessee's TENNLab, for example, has partnered with the Air Force Research Laboratory, the Army Research Laboratory, the Naval Research Laboratory and Sandia National Laboratories.

Experience. As a rough guide, engineers moving in from adjacent fields often bring 2 to 5 years of work in chip design, FPGA development, embedded machine learning or deep learning research. Postdoctoral appointments at national labs are another route into the field.

Technical skills to build:

• Spiking network modeling: leaky integrate-and-fire and related neuron models, spike encoding schemes, synaptic plasticity rules and surrogate-gradient training.
• Deep learning foundations: PyTorch, model compression and quantization, and the conversion of conventional networks into spiking form.
• Neuromorphic toolchains: the open-source Lava framework, which supports Intel's Loihi, plus simulators used to prototype networks before they reach hardware.
• Hardware design: Verilog or SystemVerilog, digital verification, FPGA prototyping, and for analog roles, circuit simulation and layout awareness.
• Measurement: power and latency instrumentation, benchmarking discipline and statistics good enough to defend a comparison in peer review.
• Systems programming: Python and C or C++, Linux, and enough networking to move event streams between sensors, hosts and boards.

Credentials. No certification is a standard requirement for this work. Employers judge candidates on publications, open-source contributions, chip tape-outs and demonstrations on real neuromorphic hardware. Access to that hardware matters, and time on a university or lab platform is a practical advantage.

Soft skills. The field is small and interdisciplinary. Engineers who can explain spike timing to a mission engineer and power budgets to a neuroscientist, and who report negative results honestly, are better placed to build lasting collaborations and win the next round of funding.

Neuromorphic engineering is a research-driven field with deep federal roots. BLS does not count neuromorphic engineers. The nearest occupation, Computer Hardware Engineers, had 76,100 workers in 2025 according to O*NET, which rates its projected growth from 2025 to 2035 as "much faster than average (7% or higher)," with about 4,100 openings a year on average. Those figures describe all hardware engineering; neuromorphic roles are only part of that occupation.

The hardware has scaled. Intel announced Hala Point on April 17, 2024, packaging 1,152 Loihi 2 processors in a six-rack-unit chassis. Sandia National Laboratories received the system in early 2024, with 1.15 billion artificial neurons, and Sandia reports that its team fit the entire FlyWire connectome, a wiring map of a fruit fly brain, onto 12 Loihi 2 chips, running more than 100 times faster than numerical simulations on conventional hardware. In March 2025, Sandia added NERL Braunfels, a SpiNNaker2-based system housing 175 million neurons, which the lab said will explore how neuromorphic computing can affect nuclear deterrence missions.

Federal programs fund visible parts of the work. The Department of Energy's Advanced Scientific Computing Research program listed "Neuromorphic and Microelectronics / Memory Computing Testbeds" among its testbeds and "Hardware Architectures and Neuromorphic Computing" among its computer science portfolios in a March 2026 program overview. One active DOE award, Neuromorphic Computing Circuit Primitive Testbeds, has a project period running from June 1, 2025 to May 31, 2030 and includes Pacific Northwest National Laboratory on its team. The Air Force Research Laboratory describes neuromorphic processors at around 100 mW as a way to enable 24/7 operations for small satellites and rovers, and says its partnership with Intel gives access to the Loihi 2 research chip and the Lava framework.

AI is reshaping the agenda. Energy is the field's pitch: Sandia's LabNews wrote in June 2025 that next-generation computing "pushes the boundaries of power consumption and cooling, increasing urgency to develop energy-efficient hardware and algorithms." Some researchers are also adapting mainstream AI architectures to spiking hardware. An Oak Ridge National Laboratory project on spiking transformers says the lab's first-phase role is to develop the spiking attention mechanism using the SuperNeuroMAT simulator, with the aim of spiking foundation models tied to DOE's Genesis Mission. For engineers on such projects, modern deep learning sits on top of neuron models and circuits in the required skill set.

The caveat. Commercial demand is still unproven. IEEE Spectrum wrote in February 2025 that despite decades of research and growing private-sector interest, "most demonstrations remain small scale and the technology has yet to have a commercial breakout." Positions funded through grants or lab programs depend on those budgets continuing.

Pay. Because the title has no BLS series, the band on this page uses Computer Hardware Engineers. Researchers whose work is mostly spiking algorithms rather than silicon may find their pay closer to research scientist scales, and lab positions follow each institution's own salary structure.

Where careers go. Engineers who build depth in both spiking models and hardware can move into lead roles on chip programs, principal investigator positions at national labs, or edge AI and low-power sensing work at semiconductor and defense companies. The skills also transfer to conventional AI accelerator design, embedded machine learning and computational neuroscience if neuromorphic funding tightens.

Dear Hiring Committee,

I am applying for the Neuromorphic Engineer position in your brain-inspired computing group. I am finishing a master's degree in computer engineering, and my thesis focused on running a keyword-spotting spiking network on a neuromorphic research board while holding accuracy close to a conventional baseline.

The thesis taught me where this work gets hard. Training the network was the easy part. Mapping it onto the chip forced me to rethink the encoding twice, because my first design overflowed on-chip memory and the second dropped spikes under heavy input. I ended up writing a small partitioning tool that balanced neurons across cores and logged spike traffic per core, which made the bottlenecks visible. I also built a measurement harness that recorded energy and latency for the board and for a GPU running the same task, so every comparison in my thesis used the same inputs and the same timing method. My advisor now uses that harness for two other projects in the lab.

Before graduate school, I spent two years as an FPGA engineer at a sensor company, where I wrote and verified Verilog for an image-processing pipeline. That experience is why I care about bring-up details: clock domains, test vectors and the unglamorous scripts that keep a lab board usable day after day.

Your group's work on event-based sensing for low-power platforms is exactly where I want to build a career. I would bring hands-on experience across the stack, from spike encoding to RTL, and a habit of reporting results, good or bad, with the measurements to back them up.

Thank you for your time and consideration. I would welcome the chance to talk about how I could contribute to your team.

Sincerely, Jordan Ellis