Lithography Engineer Job Description

Every layer of a chip starts as a pattern of light. A Lithography Engineer is responsible for printing that pattern: a photomask, or reticle, is imaged through a scanner onto a wafer coated with photoresist, the exposed resist is developed on a track, and the result is measured before the wafer moves on to etch or implant. The engineer owns the tools, recipes and control systems that keep that sequence on target, layer after layer and shift after shift.

The work divides along three lines. The first is the exposure equipment: deep ultraviolet (DUV) immersion and dry scanners, extreme ultraviolet (EUV) systems on leading-edge layers, and the coat-and-develop tracks linked to them. Lithography engineers qualify tools after preventive maintenance, match scanners to each other so a lot can run on any of them, and chase the causes of focus drift, stage errors and lens heating. Hardware repair may sit with equipment engineers or vendor field service teams, but the lithography engineer decides whether a tool is fit to run product.

The second is the process itself: resist and anti-reflective coatings, bake temperatures, exposure dose and focus, and development. A new layer gets a focus-exposure matrix to find its process window, then a recipe, then a control plan. Engineers set the rework rules that decide when a lot is stripped and recoated instead of sent to etch, and they disposition lots that land outside limits.

The third is control. Overlay, meaning how well each layer lines up with the one beneath it, and critical dimension (CD), the printed width of a feature, are measured on sampled wafers with optical overlay tools and CD-SEMs. Those measurements feed run-to-run controllers that adjust the scanner for the next lot. Purdue University's introductory nanolithography course describes this territory as in-scanner and on-wafer metrology and control loops. At the leading edge the list of problems grows: the 2024 lithography chapter of the IEEE International Roadmap for Devices and Systems (IRDS) says that improving stochastic effects such as line edge roughness and defects, critical dimension uniformity and edge placement error will be more challenging than resolution itself.

A lithography engineer works with the optical proximity correction (OPC) and mask teams who decide what goes on the reticle, the integration engineers who own the full process flow, the etch engineers who receive the developed pattern, the yield and defect teams who trace killer defects back to a layer, and the technicians and operators who run the bay. Deliverables are concrete: qualified recipes, scanner matching reports, statistical process control (SPC) charts with out-of-control action plans, engineering change requests, and root-cause reports when a lot is scrapped.

Production fabs run continuously, so engineers carry on-call rotations and suit up for the cleanroom when a scanner goes down overnight. The vocabulary of the job comes from optics and photochemistry: numerical aperture, illumination pupils, depth of focus, dose, resist contrast and mask error. An engineer who can read a scanner's lens and stage logs, set up a designed experiment on a new resist, and explain an overlay excursion to an integration manager in plain terms is doing the job well.

The usual entry point is a bachelor's degree in electrical, chemical or materials engineering, physics, or microelectronic engineering. As a rough guide, a master's degree or PhD helps for roles in process development, OPC modeling or research fabs, where the work leans on imaging theory and resist chemistry.

A few universities teach lithography directly. Rochester Institute of Technology's Microelectronic Engineering BS is a five-year program that adds chemistry, physics, materials science, optics and imaging to an electrical engineering core and includes nearly a year of cooperative education. RIT's graduate Microelectronics Manufacturing Engineering program includes a course titled Lithography Materials and Processes, which covers the chemistry of microlithography and resists. Purdue University offers a three-course nanolithography series; the first course covers diffraction-based imaging, the subsystems of modern exposure tools, and the role that digital twins and computational lithography play in the field.

Beyond the degree, the skills that matter are specific:

• Optics and imaging: partial coherence, illumination settings, depth of focus, and how mask features print.
• Resist and materials: coat, bake and develop chemistry, reflectivity control, and resist outgassing and contamination.
• Statistics: design of experiments, SPC, gauge studies for metrology tools, and lot-level data analysis in JMP or Python.
• Fab systems: the manufacturing execution system (MES), SPC and fault detection software, and run-to-run advanced process control (APC).
• Cleanroom practice: gowning, wafer handling, and working beside field engineers on a scanner that is down.

As a rough guide, new graduates start on sustaining work for mature DUV layers or as shift engineers, and taking ownership of EUV layers, scanner matching or OPC model calibration typically takes 3 to 5 years. Engineers who arrive from physics or optics backgrounds may spend their first months learning fab systems and change control; chemical engineers may spend them learning scanner hardware.

Fab lithography work does not call for an engineering license. Two optional credentials fit the job's statistical side: the Certified Six Sigma Green Belt and the Certified Six Sigma Black Belt, both from ASQ. Expect formal training on the specific scanner and track platforms your fab runs, plus internal certification before you can release recipes or disposition lots on your own.

SPIE, the international society for optics and photonics, runs conferences on lithography. Its Photomask Technology + Extreme Ultraviolet Lithography conference is where Intel Foundry and ASML presented High NA EUV updates in September 2026. Reading the proceedings keeps an engineer current, and presenting a process result there is one way to build a reputation outside one company.

BLS does not count lithography engineers separately. In May 2025 it counted 2,910 people in the Engineers, All Other occupation within semiconductor and other electronic component manufacturing, out of 154,070 in that occupation nationally. O*NET rates the broader group's projected growth as average (3% to 4%) for 2025 to 2035, with about 8,800 openings a year on average. Those numbers cover a residual group with many specialties, so they say little about lithography alone. Four developments by late 2026 show where the technical side of this work is heading.

High NA EUV reached production. Intel Foundry said on Sept. 7, 2026 that High NA EUV continues to be used in high-volume manufacturing at Intel, on select layers for a subset of its Core Ultra Series 3 processors, code-named Panther Lake, built on Intel 18A. Intel reported that overlay, throughput and availability were meeting its expectations, and its tools include an ASML EXE:5000 in Fab 25 in Oregon. The engineering agenda is specific: Intel is working on reticle stitching, which it describes as letting designers use High NA EUV with today's standard 6-inch masks, and on a transition to 6x12-inch masks. The IRDS 2024 lithography chapter notes that stitching two separate exposures requires tight overlay and CD control at the boundary unless an exclusion area is defined, which is lithography engineering work.

EUV moved into memory. Micron's annual report for fiscal 2025 says the company began shipping its 1-gamma DRAM node in 2025, its first DRAM node incorporating EUV lithography.

Resist is changing. Lam Research says it introduced dry resist technology in 2020 and that its Aether dry resist process uses a series of Lam tools before and after high-NA EUV exposure. A fab that adopts a deposited resist changes its coat and develop steps, its defect sources and its rework rules, and the lithography engineer owns those changes.

Computational lithography is moving to GPUs. On Oct. 14, 2026, Siemens announced a collaboration with NVIDIA that brings NVIDIA cuLitho acceleration to full-chip OPC in its Calibre software, aimed at making inverse lithography technology (ILT) practical for High NA EUV masks.

For a job seeker, these programs point to a skill set: EUV process experience, overlay and stitching control, comfort with OPC and simulation output, and the statistics to defend a recipe change. Engineers with DUV backgrounds can build toward that through internal moves onto EUV layers, graduate coursework in nanolithography, and SPIE conference work. The work happens where wafers are patterned or where patterning equipment and materials are built: production fabs, research fabs, toolmakers and materials suppliers. Expect to live near one of them.

Advancement runs in two directions. One is technical: senior or principal lithography engineer, module owner for a layer family, or a move into OPC and computational lithography. The other is management: lithography area manager or process engineering manager. A third path leads to applications and customer support roles at toolmakers and materials suppliers, on the other side of the same scanner.

Dear Hiring Manager,

I am applying for the Lithography Engineer opening on your EUV module team. For the past four years I have been a lithography process engineer at a 300 mm logic fab, owning two DUV immersion layers and, since last year, one EUV contact layer.

My first project was scanner matching. Our immersion scanners had drifted apart on overlay, which forced dedicated routing for critical lots and created queue time at the bay. I built a matching procedure with our metrology team, ran it after every preventive maintenance, and wrote the control limits that let the area return to open routing. The work taught me to treat a matching report as a production document, not a one-time study.

On the EUV layer I led the process window work for a resist change requested by integration. I designed the focus-exposure experiments, worked with the etch engineer to confirm the post-etch CD, and partnered with our OPC team when a pitch-walking signature appeared at the edge of the window. We released the new recipe on schedule, and I wrote the out-of-control action plan that the shift engineers now use.

I am comfortable in the cleanroom at night when a tool is down, and I am equally comfortable presenting overlay data to a yield review. I use JMP and Python every day to pull lot data from our SPC system, and I completed a graduate course in nanolithography last spring.

Your team's work on High NA layers is the reason I am writing. I would welcome the chance to bring disciplined process control and clear communication to that effort, and I would be glad to walk you through my matching and process window data in an interview.

Sincerely, Jordan Avila